Opportunities in Japan

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

We are looking for a person ready to take up the challenge of working in a high-profile project where we integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better.

In this role, you will ensure functionality and performance of the system.

This role is based out of Tokyo, Japan and offer flexible Hybrid work style.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Responsibilities:

• Verify Tenstorrent’s digital IP and SoC logic at chiplet integration level, using industry standard verification methodologies

• Build and improve components of verification infrastructure including model builds and simulation/regression runs,

• Create verification components like testbenches, checkers and test generators,

• Add assertions and coverages along associated methodologies,

• Build verification test plans for subsystems, align them with project stakeholders, implement test suites, summarize the results and share feedback with project stakeholders

• Publish and review verification metrics and drive convergence towards tape-out,

• Work across boundaries with architects, software and design/emulation teams,

• Guide and mentor junior engineers.

Experience & Qualifications:

• Advanced degree in electrical, computer engineering or computer science

• Proven experience in CPU or SoC verification

• Over 10 years of experience with verification flows, scripting and automation

• Good knowledge of logic design

• Knowledge of Verilog//v2k/system Verilog

• Strong problem solving skills

• Excellent organizational and communication skills

• Good English language skills (written and spoken)

Nice to Have:

• Knowledge of RISC-V, machine learning, die-to-die, memory controllers, PCIe, UCIe

• Knowledge of low level drivers and firmware in C

• Fluency in Japanese

• Japanese work visa

テンストレントジャパンについて

経済産業省を始めとする日本政府は予算、税制、政策のあらゆる面で世界と競争できるよう投資パッケージを準備しています。2024年にはテンストレントが持つ技術力、経験、人材が評価され、全国規模のプロジェクトを推進するための主要パートナーの 1 つに選ばれました。(詳細はこちらをご覧ください)　日本の半導体産業をより盛り上げるために様々な人材を募集しています。テンストレントジャパンや採用については人事担当（recruiting-jp@tenstorrent.com）までご連絡ください。

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.