Opportunities in Mountain View, United States

Full Job Description

You will be part of the design team driving many facets of high performance, high bandwidth designs. The tasks will include working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis, and System on Chip (SOC) integration on different subsystems. Throughout the program you will be interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. 12+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure. 10+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs. 8+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug 8+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic D2D IP design experience Fabric design experience CPU and/or graphics core design experience Complex algorithmic designs for AI usages experience Script development experience