AMD Plans Native UCIe Chiplet Connectivity for Versal RF

Versal RF is becoming a chiplet platform, but the hardware is still upcoming

AMD announced on August 25, 2026 that select Versal RF Series adaptive SoCs will gain native UCIe 1.1 connectivity for direct communication with co-packaged specialized chiplets.

This is a roadmap announcement rather than a shipping-product update. AMD says production chiplets for the planned configuration are expected with select Versal RF devices in the fourth quarter of 2027.

The move matters because UCIe provides a standardized in-package link for combining different kinds of silicon. Instead of forcing RF conversion, AI acceleration, CPUs, GPU-class specialized compute, security, communications and application-specific logic into one monolithic die or across slower board-level links, designers can place specialized chiplets in the same package.

Up to six UCIe interfaces and multi-terabit in-package bandwidth

AMD says select Versal RF devices will support as many as four UCIe-SP interfaces for standard packaging and two UCIe-AP interfaces for advanced packaging. The company describes the resulting aggregate in-package bandwidth as multi-terabit per second.

Versal RF already combines high-resolution RF data converters, dedicated DSP intellectual property, AI Engines and programmable logic. AMD says the devices provide up to 80 TOPS of heterogeneous DSP compute. Native UCIe is intended to let that base platform connect directly to additional chiplets optimized for AI, CPU, GPU, RF, optical, communications, security or custom ASIC workloads.

For AI and signal-processing systems, that could make it easier to pair domain-specific acceleration with programmable RF and DSP resources without redesigning the entire SoC.

AMD is positioning UCIe against board-level serialized links

AMD says moving selected functions into the same package can reduce latency, power, physical size, development cost and complexity compared with some board-level integrations. It specifically compares expected UCIe behavior with AMD adaptive SoCs using board-level GTM2 serialized interfaces.

Those power and latency comparisons are AMD internal analyses, not independent system benchmarks. Real benefits will depend on the final chiplets, packaging technology, memory architecture, software stack, workload, thermal design and vendor interoperability.

UCIe's open-standard design is still strategically important because it creates a common physical and protocol framework for heterogeneous chiplets from multiple suppliers. The harder production questions will be around qualified interoperability, packaging yield, thermal management and software integration.

Why this matters for future AI infrastructure

AI systems are increasingly heterogeneous. Training, inference, networking, sensor processing and security can have very different compute and data-movement requirements. Chiplets let system designers combine purpose-built silicon while reusing proven IP instead of creating a new monolithic processor for every product.

AMD's Versal RF announcement extends that trend into adaptive RF, networking and communications platforms where AI acceleration may need to sit close to data converters and deterministic DSP logic.

The key status distinction is that the UCIe-enabled platform is announced for future production, not broadly available today. Buyers should wait for final device specifications, compatible chiplets, validated interoperability and shipping systems before treating the roadmap figures as deployed capability.