Architect Labs Unveils Redwood, an AI-Designed Accelerator Built in Under Two Weeks

Architect Labs says AI designed Redwood end to end

Architect Labs announced Redwood on August 27, 2026, describing it as a frontier AI accelerator whose architecture, RTL, verification environments, formal artifacts, firmware, drivers and custom compute kernels were generated and co-optimized by its internal AI system from a high-level specification written by two human chip architects.

The company says the end-to-end design loop took under two weeks and required no human intervention below the specification layer. That is materially different from using an LLM as a coding assistant inside a conventional chip program: Architect Labs says its system regenerated and reverified entire architectural iterations, with software and hardware co-designed in the same optimization loop.

This is an important claim, but it needs a careful distinction between what is measured today and what remains projected or upcoming.

What is running now

A scaled-down Redwood Nano configuration is deployed on an AMD Versal VPK180 FPGA at 250 MHz. Architect Labs says this 2x2-tile version runs Qwen3-0.6B end to end, including prompt transfer and token streaming back to the host.

The company reports 12.1 tokens per second on that FPGA implementation. It also says it demonstrated the AI-designed accelerator running live model inference at the 2026 Design Automation Conference.

Redwood uses a tile-based spatial-dataflow architecture. Each tile combines a RISC-V control core with transformer-oriented matrix and vector compute engines, 512 KB of local memory, and a custom on-chip network. The design uses INT8 MAC arrays for matrix operations and software scheduling to coordinate data movement and computation.

Architect Labs further says that 100% of the RTL, UVM verification environments, formal verification artifacts, firmware, drivers and custom kernels were generated by its AI system from the human-authored specification. Every architectural iteration was reportedly regenerated, reverified and redeployed to FPGA within 48 hours.

The ASIC performance numbers are projections, not silicon measurements

Architect Labs projects that a Redwood ASIC built at the same process class as NVIDIA's Jetson Orin Nano would deliver 1.75x decode throughput at 1.9x lower power, or roughly a 3.4x performance-per-watt gain, against the company's measured Jetson baseline running the same model.

Those are company-reported projections, not results from a fabricated Redwood ASIC or an independent benchmark. The current physical implementation is on FPGA.

The company explicitly says real silicon remains the final ground truth and that it is continuing the flow toward full GDSII and a future TSMC tapeout. Until fabricated silicon is tested, the projected ASIC throughput, power and area advantages should not be treated as production hardware performance.

Automated verification is central to the claim

Chip generation is only useful if the design can be verified. Architect Labs reports that every block through the SoC level reached at least 95% code and functional coverage using commercial EDA tools, a proprietary formal engine and hardware-in-the-loop validation.

The company says the first RTL drop from simulation to FPGA contained zero bugs and that its AI system peaked at 115 merge commits in a single day while bringing workloads online and optimizing firmware and kernels.

These results are significant because hardware verification is normally one of the most labor-intensive stages of chip development. However, the coverage and bug-count figures are reported by Architect Labs and have not been independently audited in the announcement.

AI optimizing the silicon that runs AI

Architect Labs also describes an early recursive optimization experiment. It deployed Qwen3 on Redwood, exposed the model as an API endpoint to its own design system, and says the model found timing and kernel optimizations for a later Redwood generation.

The company calls this an early step toward recursive self-improvement, while acknowledging an important limitation: there is still a gap between the large AI systems capable of designing frontier hardware and the smaller models that can run on the current accelerator.

Released versus upcoming

Available and demonstrated now: Architect Labs has published the Redwood architecture and technical description, and a scaled Redwood Nano implementation is running multi-billion-parameter-model workloads on FPGA hardware.

Not yet demonstrated as fabricated silicon: the projected Samsung 8 nm-class performance and power results are estimates. Architect Labs says its next work includes physical design, full GDSII, tapeout, larger models and post-silicon validation.

Redwood therefore should not be described as a shipping ASIC. The genuinely new development is the public demonstration of an AI-generated accelerator stack running real inference on programmable hardware, together with the company's disclosed automated design and verification workflow.

Why this matters

AI hardware is usually constrained by long design cycles measured in years. If end-to-end AI systems can reliably explore architecture, generate RTL, close verification, co-design firmware and kernels, and repeatedly deploy working hardware in days, custom accelerators could be adapted to changing model architectures much faster.

Redwood does not yet prove that autonomous chip design can replace mature production silicon flows. It does provide a concrete, hardware-running test of how much of the design-and-verification loop can be automated, making it a notable development at the intersection of AI agents, EDA and AI infrastructure.