Cerebras Previews CS-5 for 2027 and CS-6 with Wafer-Scale 3D Memory

Cerebras has outlined the next two generations after CS-4

Cerebras used Hot Chips 2026 on August 25 to reveal more detail about its current CS-4 system and, more importantly, preview the architecture roadmap behind CS-5 and CS-6. The company positions its Nexus rack-scale platform as a reusable infrastructure base that can carry multiple generations of wafer-scale systems without redesigning every power, cooling and I/O component from scratch.

CS-4 is already the first system built on Nexus. The new information is forward-looking: Cerebras says CS-5 is targeted for 2027, while CS-6 is being designed around wafer-scale 3D memory integration. These are product targets and roadmap claims, not shipping specifications.

Nexus makes the compute module replaceable

A Nexus rack supports three Wafer-Scale Engines, each installed in a modular compute backpack at the rear of the rack. Each backpack carries its own compute, water conditioning, monitoring, power interfaces and I/O.

Cerebras says this separation is intended to let datacenters install the shared rack infrastructure first and then replace or upgrade compute modules independently. The same chassis and service model can therefore support later processor generations if the roadmap ships as planned.

CS-4's power delivery also moves conversion hardware unusually close to the wafer. Cerebras says AC/DC converters sit roughly 0.5 millimeters from the processor rather than tens of millimeters away, reducing resistive losses in the final delivery path. Those engineering details are vendor-described and should be validated against real datacenter operating data as deployments scale.

CS-5 targets extremely high per-user token rates

For CS-5, Cerebras says its 2027 target is up to 10,000 output tokens per second per user on leading open models such as Gemma 4 31B and gpt-oss-120b. For much larger multi-trillion-parameter systems, including examples such as Kimi and GPT-5.6 Sol, Cerebras targets up to 5,000 output tokens per second per user and 3 million tokens per second per megawatt.

The company also says the architecture is intended to support models above 50 trillion parameters while maintaining interactive generation speeds. These numbers are explicitly roadmap targets rather than independently measured shipping performance. Cerebras includes forward-looking-statement language in the announcement, so they should not be treated as guaranteed launch specifications.

The practical motivation is agent latency. A long-running agent often makes many model calls sequentially; reducing decode time at every step can shorten total task completion even if the agent's reasoning algorithm does not change.

CS-6 is designed to stack DRAM with wafer-scale compute

The more unusual roadmap item is CS-6. Cerebras says it began developing the concept in 2024 and plans to combine wafer-scale SRAM and compute with 3D-stacked DRAM connected through very high-bandwidth links.

Wafer-scale processors already occupy the practical two-dimensional area limit, so Cerebras is looking upward for additional memory capacity. The goal is to keep more of a large model physically close to the compute wafer rather than spreading it across a larger number of separate systems.

If the design works as intended, the company argues that tightly integrated DRAM could reduce the number of systems required for very large models and shrink the infrastructure footprint for ultrafast inference. No shipping date, final memory capacity or commercial specification for CS-6 was provided in the Hot Chips post.

The roadmap doubles down on scale-up inside one wafer

Cerebras's architectural bet differs from conventional multi-accelerator racks. GPU systems scale by connecting many processors over external fabrics; Cerebras tries to keep the highest-volume communication on one wafer and move only lower-volume data between systems when models span multiple wafers.

The company compares aggregate on-wafer bandwidth with rack-level external fabrics, but direct bandwidth numbers across fundamentally different architectures do not by themselves establish application-level superiority. Actual performance depends on model structure, batch size, memory placement, compiler/runtime efficiency, power limits and deployment topology.

The meaningful news from Hot Chips is the direction of travel: CS-5 focuses on another large jump in decode speed, while CS-6 attempts to extend wafer-scale computing into the third dimension with stacked memory.

For infrastructure teams, the timeline is equally important. CS-4 is the current announced system, CS-5 is a 2027 target, and CS-6 is a longer-term architecture under development. Capacity planning should distinguish those stages rather than treating the full roadmap as available hardware today.