Principal Design Verification Engineer

Full Job Description

The AISoC silicon team is seeking a passionate, driven, and intellectually curious computer/electrical engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property (IP) and System on Chip (SoC) designs that can perform complex and high-performance functions in an extremely efficient manner. Technically lead a pre-silicon verification team for the development of custom IP components with focus on architectural and micro-architectural based functions and features. Interact with architects and design engineers to create testplans covering verification strategy, test requirements, and test environments for IP verification. Write, execute, enhance, and debug constrained random stimulus, scoreboards and checkers, and assertions to verify design correctness. Develop Universal Verification Methodology (UVM) components to interface between test code and verification simulation environments. Collaborate across verification teams on vertical and horizontal reuse of components. Define and implement functional coverage and drive coverage closure. Triage and debug testbench, simulation, and emulation fails. Write makefiles and scripts for verification infrastructure. Apply Agile development methodologies including code reviews, sprint planning, and feature deployment. Provide technical leadership through mentorship and strong teamwork. Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. Other: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 12+ years of experience in design verification Experience with verification for multiple product cycles from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C++ and Universal Verification Methodology (UVM) Experience debugging Register Transfer Level (RTL) designs as well as simulation and/or emulation environments. 5+ years experience with lead roles across cross-functional / cross-time-zone engineering teams. Verification lead experience for an IP or SS related to CPUs, VPUs, GPUs, Direct Memory Access (DMA) engine, Tensor unit, or similar Experience of working on Artificial Intelligence (AI) / Machine Learning (ML) SoCs Experience in Scripting language such as Python or Perl Hands on experience in Formal property verification

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