Principal Hardware Architect

Full Job Description

Architecting and development of memory controllers Reviewing Memory technology roadmaps including, but not limited to: DDR5, DDR6, LPDDR, HBM, Type 3 CXL-based Memory, RDIMM, MRDIMM, LP-MRDIMM, and emerging memory technologies Working closely with memory controller micro-architects, verification and validation to drive features into production Working with Vendors evaluate IP and make recommendations Work with Performance Modeling team to develop cycle approximate model of the controller and also analyze SOC/platform Azure workload results Working closely with Strategic Planning and Architecture as well as internal customers to understand workload and use case requirements with specific focus on identifying full stack optimization opportunities within the context of the overall memory hierarchy Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience OR equivalent experience. This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. Delivered Architecture, Design or Verification specs for multiple generations of Memory Controllers Familiar with DDR, HBM or LPDDR JEDEC specs Experience in SoC memory hierarchy/architecture, and knowledge of emerging memory technologies.

Verified from public schema.org JobPosting structured data on the official source page. The complete published description, responsibilities, requirements and benefits were normalized when present; unstated facts were not inferred.