Overview
We are seeking a highly skilled and experienced Physical Design Engineer to join our dynamic team. As a key member of our semiconductor design team, you will be responsible for physical design implementation and physical integration efforts to ensure the successful development of cutting-edge semiconductor products. As a Principal Physical Design Engineer, you will be responsible for Physical Design tasks at block, subsystem, sub-chip, and/or full-chip level. The tasks will include Floorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM. You may also be involved in Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection. Expected to drive PD team at block/Sub System / Sub Chip / SOC level to set and deliver quality r
Full job description
Full Job Description
We are seeking a highly skilled and experienced Physical Design Engineer to join our dynamic team. As a key member of our semiconductor design team, you will be responsible for physical design implementation and physical integration efforts to ensure the successful development of cutting-edge semiconductor products. As a Principal Physical Design Engineer, you will be responsible for Physical Design tasks at block, subsystem, sub-chip, and/or full-chip level. The tasks will include Floorplanning, Synthesis, Placement, CTS and custom clocking, Routing, Static Timing, Physical Verification, Formal Equivalency, Power Efficiency, IR-Drop, and EM. You may also be involved in Physical Design flow development/automation and evaluation of and recommendations for technology, IP, and vendor selection. Expected to drive PD team at block/Sub System / Sub Chip / SOC level to set and deliver quality results as per planned milestone goals. You are expected to be able to work with limited direction, have keen attention to detail, and be able to provide crisp status of progress, issues, and risks on the program to the management team. Occasional travel may be required. Bachelor's or master's in electrical or computer engineering or related field with 12+ years of experience Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level. Experience in tapeouts of complex ASICs in leading edge technology Experience in leading team to deliver planned PD goals.
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