Senior SerDes & Analog Layout Design Engineer

Full Job Description

Drive physical implementation of complex D2D SerDes and analog/mixed-signal IP in advanced process technologies, from floorplanning through tapeout, signoff, and integration. Own or co-own top-level D2D analog front-end floorplanning and integration, including partitioning, hierarchy, die-edge constraints, bump or micro-bump alignment, ESD interfaces, power distribution, sensitive routing, and package-aware implementation tradeoffs. Establish matching and parasitic-control strategies for critical circuits using symmetry, common-centroid placement, interdigitation, device orientation control, dummy structures, shielding, guard rings, isolation, return-path planning, and gradient mitigation. Help lead D2D layout execution across multiple blocks and contributors by defining implementation plans, coordinating technical work, reviewing layouts, resolving cross-block dependencies, and supporting milestone closure. Partner with circuit design leadership to translate electrical requirements into physical implementation constraints and make layout-versus-circuit tradeoffs that improve system-level power, performance, area, signal integrity, reliability, and yield. Identify and resolve layout risks for high-speed transmitter, receiver, clocking, bias, equalization, PLL/DLL, and related analog front-end circuitry. Collaborate across signal integrity, package, ESD, physical design, CAD, foundry, reliability, and SoC teams to align interface definitions and integration requirements for the assigned subsystem. Own physical verification and signoff closure, including DRC, LVS, ERC, antenna, density, extraction review, EMIR, reliability analysis, layout-dependent effects, and complex cross-hierarchy debug. Contribute to layout quality criteria, review checklists, release requirements, and signoff evidence for internally and externally developed D2D and analog IP. Deliver production-ready IP collateral, including GDS/OASIS, LEF abstracts, integration views, interface documentation, waiver rationale, review records, and signoff packages for SoC and package integration. Develop and improve analog layout methodologies, reusable templates, automation flows, and productivity solutions using SKILL, TCL, Python, or similar scripting languages. Provide technical guidance and mentorship through design reviews, coaching, documentation, and sharing of advanced-node analog and D2D layout practices. Coordinate technical execution with contractors, vendors, and geographically distributed design partners by setting expectations, reviewing quality, resolving issues, and supporting program commitments. Communicate technical status, risks, tradeoffs, and recommendations to engineering and program stakeholders for assigned D2D deliverable Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. Other: This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate's citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable. 5+ years of analog or mixed-signal layout experience, including matching-critical transistor-level layout in advanced process technologies. Experience owning significant analog or mixed-signal layout deliverables through physical verification, signoff, and tapeout. Experience using Cadence Virtuoso and Siemens/Mentor Calibre physical verification tools. Experience with DRC, LVS, ERC, antenna, extraction-aware layout, and advanced-node physical signoff. Experience collaborating across circuit design and physical implementation teams and providing technical guidance or design reviews to other layout contributors. Experience with high-speed SerDes, D2D interfaces, or comparable high-performance analog/mixed-signal IP, including transmitter, receiver, clocking, bias, equalization, PLL/DLL, or related circuitry. Deep understanding of analog matching, symmetry, layout-dependent effects, device orientation, process gradients, coupling, isolation, shielding, return paths, and parasitic optimization. Familiarity with D2D standards or implementations such as UCIe, BoW, or proprietary die-to-die links. Experience with advanced packaging and chiplet integration, including die-edge planning, bump or micro-bump interfaces, ESD structures, package escape, power delivery, and signal-integrity constraints. Experience influencing floorplan, interface, or circuit decisions based on physical implementation feasibility and extracted-layout results. Experience leading top-level assembly and verification of analog subsystems containing blocks developed by multiple engineers or external partners. Experience with EMIR and reliability signoff using Ansys Totem, Cadence Voltus, or equivalent tools. Experience with Cadence automated place-and-route (APR) flows, including floorplanning, placement, clock or signal routing, physical optimization, and integration of custom analog or mixed-signal IP with digitally implemented logic. Experience with FinFET and/or Gate-All-Around technologies and advanced nodes such as 5nm, 3nm, or beyond. Demonstrated ability to mentor engineers, lead technical reviews, and resolve complex layout issues across team boundaries. Experience managing technical execution with geographically distributed teams, contractors, vendors, or design-service partners across multiple milestones or programs.

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