Verified current Job

Senior Silicon Engineer

ABOUT THE ROLE

Job Full source details
Clera San Francisco Source published Oct 1, 2026 Verified 5 hours ago
✓ 100% verification score · Source: Clera (ashby) · Always confirm final requirements on the original source.
Complete source information imported The available role or programme description, requirements, benefits and source facts were imported from the public official endpoint and formatted for reading.
EmploymentFull-time

Overview

ABOUT THE ROLE

Full job description

ABOUT THE ROLE As a founding silicon team member at a well-funded AI accelerator startup, you will lead the full journey of a custom XPU from FPGA prototype through tapeout and bring-up. This is a high-ownership, high-impact role that sets technical direction across architecture, RTL, verification, and tooling while the silicon organization grows around you. WHAT YOU'LL DO

  • Lead FPGA prototype development and optimization of the XPU, taking designs from specification to working silicon.
  • Design and review RTL destined for the first ASIC, ensuring clean microarchitecture and synthesizable code.
  • Build lint, simulation, synthesis, timing, and verification flows to support rapid iteration and tapeout readiness.
  • Make architecture decisions spanning compute datapaths, memory systems, on-chip interconnect, and control logic.
  • Drive the design through tapeout, bring-up, and delivery milestones, including critical-sprint periods.
  • Grow and mentor the silicon team as the company scales. WHAT WE'RE LOOKING FOR
  • 8 or more years of hands-on digital design or silicon engineering experience building RTL, FPGA prototypes, or ASICs.
  • Proven ability to ship synthesizable SystemVerilog or Verilog in production silicon or FPGA designs.
  • End-to-end FPGA experience: RTL through synthesis, place-and-route, and deployment to working hardware.
  • Strong fundamentals in pipelining, clocks, resets, latency, throughput, and microarchitecture.
  • Fluency with simulation, linting, synthesis, SDC constraints, timing closure, and CDC verification flows.
  • Experience automating hardware flows using Python, Tcl, Make, Nix, or similar tools.
  • Background designing or optimizing AI accelerators or low-level AI kernel implementations.
  • Tapeout experience, high-speed interface design, formal verification, UVM, cocotb, firmware, or systems programming are strong advantages.
  • Self-directed, comfortable with ownership, and energized by fast-moving environments. COMPENSATION & BENEFITS Base salary range: $200,000 to $300,000 USD annually, plus equity. Visa sponsorship is available. LOCATION Full-time, on-site in San Francisco, CA. This role is not remote or hybrid.

Tips for this job

Practical JobOpportunity guidance. These tips do not replace official rules or create new eligibility requirements.

  1. Tailor the CV and application to the responsibilities and required skills stated on the official employer page.
  2. Use concrete evidence of relevant work, projects and measurable results rather than generic claims.
  3. Confirm location, work authorization, remote restrictions and sponsorship terms before applying.
  4. Apply through the original employer or official recruitment destination shown on this page.

Verification notes

laptop-ats-crawler v3

Original authoritative source

JobOpportunity is the discovery and verification layer. Confirm eligibility, dates, salary/funding and application instructions on the original source before submitting anything.

Apply through JobOpportunity →

Browse current JobOpportunity listings from Clera (ashby) →

More ways to save

Discover deals, coupons and free courses on our sister site.

Explore DealVorio
Save more with DealVorio: deals, coupons, free courses, apps and books