Overview
Synopsys is hiring an ASIC Digital Design Staff Engineer in Yerevan for RTL design, synthesis, timing-aware implementation and cross-team hardware development.
Full job description
Job ID 17693. The current official listing requires a bachelor's or master's degree in electrical engineering, computer engineering or a related field and 4+ years of digital-design and/or RTL experience.
Requirements & qualifications
Bachelor's or master's degree in Electrical Engineering, Computer Engineering or a related field; 4+ years in digital design and/or RTL development; Verilog/SystemVerilog and ASIC-flow knowledge.
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