Jobs

Full Job Description

Annapurna Labs, an Amazon company, is seeking an exceptional an exceptional leader to build and lead our next-generation internal Analog IP design team. This is a unique opportunity to create a world-class analog design center from the ground up, developing the critical IP blocks that power all of our custom silicon products, including Graviton (server CPUs), Nitro (networking/security accelerators) and Trainium (machine learning accelerators).

At Annapurna Labs, we think big in both scale and scope. We are building internal capabilities for cutting-edge analog IP that will define the next era of cloud infrastructure silicon. This role is an opportunity to shape the analog IP strategy across all our products and lead the team that delivers it.

Key job responsibilities Build the team: Recruit, hire, and develop a world-class analog/mixed-signal design team from the ground up. Define the org structure, roles, and growth path.

Define the IP strategy: Own the analog IP roadmap across all Annapurna Labs products. Evaluate build vs. buy decisions and drive internal capability development.

Drive execution: Lead the full design cycle from architecture through silicon validation — spec, schematic, layout, simulation, tapeout, and bring-up.

Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog IP seamlessly.

Set technical direction: Define design methodologies, flows, and best practices. Evaluate and select EDA tools, PDKs, and foundry processes.

Innovate at scale: Develop IP that is reusable, portable across process nodes, and designed to meet the performance, power, and area (PPA) needs of multiple products simultaneously.

About the team Why Annapurna Labs

Annapurna Labs designs the silicon that powers AWS — the world’s largest cloud platform. Our chips (Graviton, Nitro, Trainium, Inferentia) serve millions of customers globally. You will:

Work at the intersection of analog design and hyperscale cloud infrastructure

Build a team and IP portfolio that directly impacts AWS’s competitive edge

Have access to leading-edge process nodes and world-class foundry partnerships

Collaborate with top-tier silicon architects, system designers, and software engineers

See your designs deployed at unprecedented scale — millions of instances worldwide

Basic Qualifications

• B.Sc. in Electrical Engineering.
• 10+ years of hands-on analog/mixed-signal design experience in advanced CMOS nodes (7nm and below)
• 5+ years of proven engineering management experience, including building and scaling teams
• Deep expertise in one or more: high-speed SerDes/PHY, PLL/DLL, data converters, LDOs/power management, or I/O interfaces
• Track record of successful tapeouts and silicon bring-up in volume production
• Experience with design methodologies for IP portability and reuse across multiple process nodes
• Strong understanding of semiconductor physics, device modeling, and process technology

Preferred Qualifications

• Experience with die-to-die interfaces (UCIe, HBI) or advanced packaging (2.5D/3D)
• Experience with integrated voltage regulators (IVR) for high-performance compute
• Experience leading analog IP development in a hyperscaler or large semiconductor company
• Familiarity with GPIO design for multi-standard (LPDDR, PCIe, ETH) compatibility
• Background in developing reusable IP platforms with configurable/parameterized architectures
• Experience in cloud/data center silicon or high-performance computing
• Strong publication record or patents in analog IC design

Our inclusive culture empowers Amazonians to deliver the best results for our customers. If you have a disability and need a workplace accommodation or adjustment during the application and hiring process, including support for the interview or onboarding process, please visit https://amazon.jobs/content/en/how-we-hire/accommodations for more information. If the country/region you’re applying in isn’t listed, please contact your Recruiting Partner.

B.Sc. in Electrical Engineering. 10+ years of hands-on analog/mixed-signal design experience in advanced CMOS nodes (7nm and below) 5+ years of proven engineering management experience, including building and scaling teams Deep expertise in one or more: high-speed SerDes/PHY, PLL/DLL, data converters, LDOs/power management, or I/O interfaces Track record of successful tapeouts and silicon bring-up in volume production Experience with design methodologies for IP portability and reuse across multiple process nodes Strong understanding of semiconductor physics, device modeling, and process technology