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Formal Design Verification Engineer

The candidate for this position will be expected and able to complete the following responsibilities: Own or lead verification of components used in Fabric Interconnect Learn about the design and interact with partner teams to def...

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Microsoft Raleigh, NC,US, US Source published Aug 5, 2026 Verified 8 hours ago
✓ 95% verification score · Source: Microsoft Careers · Always confirm final requirements on the original source.
Complete source information imported The available role or programme description, requirements, benefits and source facts were imported from the public official endpoint and formatted for reading.
Formal Design Verification Engineer opportunity at Microsoft
DeadlineMon Feb 1 9:30 PM 2027
EmploymentF U L L T I M E
CountryUS

Overview

The candidate for this position will be expected and able to complete the following responsibilities: Own or lead verification of components used in Fabric Interconnect Learn about the design and interact with partner teams to define verification strategies and test plans Develop Formal-based verification environments and run and debug simulations to drive quality Innovate to improve verification efficiency through methodologies or tools Apply industry leading generative AI solutions to verification work Coach and mentor others in your areas of expertise Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering,

Full job description

Full Job Description

The candidate for this position will be expected and able to complete the following responsibilities: Own or lead verification of components used in Fabric Interconnect Learn about the design and interact with partner teams to define verification strategies and test plans Develop Formal-based verification environments and run and debug simulations to drive quality Innovate to improve verification efficiency through methodologies or tools Apply industry leading generative AI solutions to verification work Coach and mentor others in your areas of expertise Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. 3+ years of pre-silicon subsystem or IP Formal verification experience. Demonstrated experience in verification of designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols Demonstrated experience in one or more of the following: fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges Experience driving IP verification for multiple product cycles from definition to silicon, including writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff Demonstrated hands-on technical leadership such as creating bottom's up schedules, coordinating work across a team, driving verification closure, or solving cross-team technical problems Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking Aptitude for writing scripts/software with industry standard languages like Python Experience applying generative AI to day-to-day tasks

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