SOC/IP Integration Engineer (eInfochips Inc)

This position is listed on behalf of a partner company, which manages all applications and next steps. Our partner is looking for a SOC/IP Integration Engineer (eInfochips Inc) based in the United States. Join a dynamic engineering environment focused on advanced semiconductor design and system-on-chip (SoC) development. As a SOC/IP Integration Engineer, you will play a key role in integrating complex subsystems and intellectual property (IP) components into reliable, high-performance chip architectures. You will work across RTL design, digital logic, verification quality checks, synthesis, and physical design handoff. Your expertise will help ensure that integrated designs meet performance, timing, and quality requirements throughout the development lifecycle. Working independently with minimal supervision, you will solve complex technical challenges, contribute to process improvements, and support the development of less experienced engineers. This fully remote opportunity combines hands-on technical ownership, customer collaboration, and exposure to sophisticated semiconductor engineering projects, with occasional travel to a client office as required.

SoC and subsystem integration: Lead the integration of system-on-chip subsystems using Verilog and SystemVerilog, ensuring that components are correctly connected and function as intended within the overall design. IP integration and fabric generation: Integrate first-party and third-party intellectual property (IP) components, generate interconnect fabrics, perform integration quality checks, and prepare designs for physical design handoff. RTL and digital design analysis: Apply a strong understanding of RTL design and digital design principles to evaluate integration requirements, identify technical issues, and develop effective solutions. Synthesis and timing optimization: Support synthesis activities, define and review timing constraints, consider floor-planning requirements, and optimize design performance to meet implementation objectives. Design quality and closure: Drive design-quality activities, including clock-domain crossing (CDC), lint, reset-domain crossing (RDC), and register integration checks, to improve reliability and ensure design readiness. Technical problem-solving: Investigate complex integration challenges, evaluate existing solutions, and apply sound engineering judgment to resolve issues efficiently and independently. Customer communication: Maintain effective communication with customers, provide clear daily or weekly progress updates, discuss technical challenges, and ensure expectations are understood and managed. Process improvement: Identify opportunities to refine integration workflows, improve engineering efficiency, and strengthen design quality throughout the development process. Technical collaboration and mentoring: Serve as a technical resource for colleagues, provide informal guidance to junior engineers, and share knowledge to support team development. Customer satisfaction: Deliver high-quality engineering outcomes, meet agreed project expectations, and contribute to successful customer engagements. Requirements Education and experience: Typically, 5–7 years of relevant professional experience with a four-year degree, or at least 3 years of experience with an advanced degree, or equivalent practical experience. RTL and digital design expertise: Strong understanding of RTL design and digital logic concepts, with the ability to analyze complex designs and resolve integration challenges. SoC and subsystem integration: Demonstrated experience integrating SoC subsystems and combining first-party and third-party IP components into cohesive designs. Hardware description languages: Practical experience with Verilog and SystemVerilog for subsystem integration and related design activities. Synthesis and physical design awareness: Knowledge of synthesis, timing constraints, floor-planning considerations, and physical design handoff requirements. Design verification and quality: Familiarity with CDC, lint, RDC, register integration, and other design-quality checks required to achieve design closure. Performance optimization: Ability to assess design performance, identify potential bottlenecks, and contribute to optimization efforts while maintaining design integrity. Problem-solving and analytical thinking: Ability to address complex technical problems, apply established solutions creatively, and exercise sound judgment when evaluating alternatives. Independent execution: Comfortable working with minimal supervision, managing technical responsibilities independently, and delivering results within project timelines. Communication skills: Strong written and verbal communication skills, including the ability to explain technical topics clearly and provide structured progress reports to customers and stakeholders. Customer orientation: Commitment to customer satisfaction, reliable delivery, and professional collaboration across engineering teams and client organizations. Leadership and teamwork: Ability to contribute to process improvements, share technical knowledge, and provide guidance to less experienced colleagues. Work arrangement and travel: Ability to work remotely within the United States and travel to a designated client office when requested by client leadership. Benefits Competitive compensation: Attractive financial compensation and access to various compensation plans. Medical coverage: Medical, dental, and vision insurance. Retirement savings: 401(k) retirement plan with matching contributions. Disability protection: Short-term and long-term disability insurance. Health savings options: Health Savings Account (HSA) and Health Reimbursement Arrangement (HRA) options. Paid time off: Paid leave, including vacation, holidays, and sick time. Tuition reimbursement: Financial support for eligible educational and professional development opportunities. Career growth: Opportunities to expand technical expertise, strengthen semiconductor integration skills, and pursue long-term career development. Remote work flexibility: Fully remote work arrangement, with occasional travel to a client office when required. Technical exposure: Opportunities to work on sophisticated semiconductor design and integration projects in a collaborative engineering environment.