Evi Technologies Limited Opportunities

Full Job Description

Join the team which delivers highly differentiated silicon into Blink and Ring battery powered devices. Our team works on state-of-the art SoCs in a vertically integrated team environment to deliver products our customers love. Innovators will be delighted with our integrated verification/validation environment that is used to perform architectural modeling to post-silicon validation. The team works backwards from customer requirements to build super-low power, energy efficient designs that include the latest in AI, video processing, low power communications and CMOS fabrication technology.

Key job responsibilities

• Write micro-architecture specs and solicit feedback/link to KPIs from architecture team
• Execute on design specifications to deliver high quality RTL
• Evaluate 3rd party IP blocks
• Estimate power, performance, and area for significant IPs early in design cycle
• Ensure quality by running and tracking results of front-end tools including: Synthesis, Lint (RTL, DFT, UPF), Power Analysis and STA
• Work with pre-silicon verification teams to assist in defining test-plans/test-benches
• Work with post-silicon validation teams to define and execute on test-plans

Basic Qualifications

• Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills
• Experience with front-end design tools (Lint, CDC, RDC and lint)
• Ability to write detailed micro-architectural specs which work through the design problems before coding (System Verilog, Verilog).

Preferred Qualifications

• Bachelor's degree in Electrical or Communications Engineering or a related field
• Experience with industry standard tools and scripting languages (Python or Perl) for automation
• Experience with hardware-software interfaces
• Using formal verification tools to enhance RTL quality before testing.

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Experience identifying bugs in architecture, algorithms, functionality, and performance with strong overall debugging skills Experience with front-end design tools (Lint, CDC, RDC and lint) Ability to write detailed micro-architectural specs which work through the design problems before coding (System Verilog, Verilog).