Overview
As a Principal Engineer on the Annapurna Labs analog/mixed-signal design team, you will be the technical authority for analog IP that powers AWS's custom silicon portfolio. You will architect, design, and deliver high-performance analog IP blocks — including high-speed SerDes/PHY, PLLs, data converters, power management circuits, and I/O interfaces — across advanced CMOS nodes for products like Graviton, Nitro and Trainium. You will drive IP reuse and portability strategies, lead silicon bring-up campaigns, and set the technical direction for the analog IP roadmap. Key job responsibilities •Drive execution: Lead the full design cycle from architecture through silicon validation — spec, schematic, layout, simulation, tapeout, and bring-up. •Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog I
Full job description
Full Job Description
As a Principal Engineer on the Annapurna Labs analog/mixed-signal design team, you will be the technical authority for analog IP that powers AWS's custom silicon portfolio. You will architect, design, and deliver high-performance analog IP blocks — including high-speed SerDes/PHY, PLLs, data converters, power management circuits, and I/O interfaces — across advanced CMOS nodes for products like Graviton, Nitro and Trainium. You will drive IP reuse and portability strategies, lead silicon bring-up campaigns, and set the technical direction for the analog IP roadmap.
Key job responsibilities •Drive execution: Lead the full design cycle from architecture through silicon validation — spec, schematic, layout, simulation, tapeout, and bring-up. •Collaborate cross-functionally: Partner with SoC architecture, digital design, physical design, DFT, packaging, and system teams to integrate analog IP seamlessly. •Set technical direction: Define design methodologies, flows, and best practices. Evaluate and select EDA tools, PDKs, and foundry processes. •Innovate at scale: Develop IP that is reusable, portable across process nodes, and designed to meet the performance, power, and area (PPA) needs of multiple products simultaneously.
Basic Qualifications
•B.Sc. in Electrical Engineering (advanced degree preferred) •15+ years of hands-on analog/mixed-signal design experience in advanced CMOS nodes (7nm and below) •Direct experience designing die-to-die (D2D) interconnect PHY — standard and/or advanced package •Deep expertise in one or more: high-speed SerDes/PHY, PLL/DLL, data converters, LDOs/power management, or I/O interfaces •Track record of successful tapeouts and silicon bring-up in volume production •Experience with design methodologies for IP portability and reuse across multiple process nodes •Strong understanding of semiconductor physics, device modelling, and process technology
Preferred Qualifications
Experience with integrated voltage regulators (IVR) for high-performance compute •Experience leading analog IP development in a hyperscaler or large semiconductor company •Familiarity with GPIO design for multi-standard (LPDDR, PCIe, ETH) compatibility •Background in developing reusable IP platforms with configurable/parameterized architectures •Experience in cloud/data center silicon or high-performance computing •Strong publication record or patents in analog IC design
Requirements & qualifications
•B.Sc. in Electrical Engineering (advanced degree preferred) •15+ years of hands-on analog/mixed-signal design experience in advanced CMOS nodes (7nm and below) •Direct experience designing die-to-die (D2D) interconnect PHY — standard and/or advanced package •Deep expertise in one or more: high-speed SerDes/PHY, PLL/DLL, data converters, LDOs/power management, or I/O interfaces •Track record of successful tapeouts and silicon bring-up in volume production •Experience with design methodologies for IP portability and reuse across multiple process nodes •Strong understanding of semiconductor physics, device modelling, and process technology
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